1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a built-in self-test (BIST) circuit.
2. Description of the Related Art
In a NAND flash memory which is one of a semiconductor memory device, write and read operations are performed in units of a page size of 512 bytes or 2 Kbytes depending on the product type. In order to enable the write or read operation to be performed in units of a page, sense amplifiers connected to bit lines one by one each serve also as a data register that temporarily holds data read from a memory cell (refer to, e.g., Japanese Patent No. 2647321).
The NAND flash memory incorporates a BIST circuit for automatically detecting the defect of a memory cell according to a sequence defined inside a product. In the BIST sequence, a bit line leak test, a bit line open test, data deletion, All Binary 0 write/read test, and All Binary 1 data write/read test (BIST) are automatically performed according to the sequence so as to detect the defect of a memory cell array.
In the All Binary 0 write/read test and All Binary 1 write/read test, after a test pattern of All Binary 0 or All Binary 1 has been written in a memory cell, the data is read to the sense amplifier in units of a page. When not all the data in a page are identical, it is determined that a read fail is detected as a defect.
However, in a conventional BIST, it has been possible to detect the defect only with a test pattern using an expectation value of All Binary 0 or All Binary 1. Therefore, detection efficiency of the defect has been low.